The present invention relates to a method of manufacturing a semiconductor device, and more specifically to a method for manufacturing a semi-conductor device using complementary resist patterns in self-alignment.
In the manufacture of a semiconductor device, e.g., an MOS transistor, resist patterns are used which are complementary to each other or in an inverse relation. For example, the complementary resist patterns are used in a process for forming an element isolation region (field oxide film) and a field inversion preventing layer thereunder.
Conventionally, the MOS transistor is manufactured by the following method including the aforesaid process.
First, a thin oxide film 2 is formed on a p-type semiconductor substrate 1, and a resist layer 3 is then applied over the whole surface of the oxide film 2, as shown in FIG. 1A. Then, those portions of the resist layer 3 which correspond to field regions are selectively removed by the photoengraving process (PEP) to form a resist pattern 4, as shown in FIG. 1B. Thereafter, a p-type impurity, e.g., boron, is ion-implanted in the surface of the semiconductor substrate 1 by the use of the resist pattern 4 as a mask, forming a p-type field inversion preventing layer 5.
Subsequently, the resist pattern 4 is peeled off, the thin oxide film 2 thereunder is removed, and then a thick oxide film 6 is formed on the whole surface of the resultant structure by heat oxidation, as shown in FIG. 1C. Then, a resist pattern 7 is formed by the PEP on those portions of the oxide film 6 which correspond to the field regions. Thereafter, the thick oxide film 6 is selectively etched by using the resist pattern 7 as a mask to form a field oxide film 8, as shown in FIG. 1D.
After the resist pattern 7 is peeled off, a thin oxide film 9 is formed on the exposed surface of the semiconductor substrate 1 by heat treatment, and a polycrystalline silicon (polysilicon) layer 10 is formed on the whole surface of the resultant structure, as shown in FIG. 1E. Thereafter, the polysilicon layer 10 is patterned to form a gate electrode 11, and then the thin oxide film 9 is selectively etched by using the gate electrode 11 as a mask to form a gate oxide film 12, as shown in FIG. 1F. Further, an n-type impurity, e.g., arsenic, is ion-implanted in the surface of the semiconductor substrate by the use of the gate electrode 11 as a mask, and n.sup.+ -type source and drain regions 13 and 14 are formed in the surface of the semiconductor substrate 1. Then, an interlayer insulation film 15 is deposited on the whole surface of the structure, and contact holes 16 are formed in those portions of the insulation film 15 which correspond to parts of the source and drain regions 13 and 14. Thereafter, wirings 17 and 18 connecting the source and drain regions 13 and 14 through the contact holes 16 are formed on the insulation film 15, as shown in FIG. 1G. Thus, an MOS transistor is completed.
According to the aforementioned manufacturing method, however, the field inversion preventing layer 5 and the field oxide film 8 are formed by using the resist patterns 4 and 7, as the masks, that are formed by different PEP's and are inevitably subject to misalignment. Therefore, it is hard to form the field inversion preventing layer 5 and the field oxide film 8 in self-alignment. As a result, the field inversion preventing layer 5 extends to the island region (element region) of the semiconductor substrate 1 which is isolated by the field oxide film 8, as indicated by a hatched section 19 in FIG. 2. If the element region is fine, there will be formed narrow channels, which cause fluctuations of threshold voltage and the like. The fluctuations will then deteriorate the element characteristics of the MOS transistor obtained. Moreover, the field inversion preventing layer 5 is not formed right below the transistor ends indicated by symbol A, permitting production of a parasitic MOS transistor.
The use of the separately formed resist patterns 4 and 7 requires two exposure processes which lower the efficiency of the production of the MOS transistor.